The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically to a semiconductor device including sidewall insulation films for interconnection layers, which are suitable to open micronized contact holes between the interconnection layers.
A DRAM (Dynamic Random Access Memory), which comprises memory cells each including one transfer transistor and one capacitor, may take a small area, and is a semiconductor memory suitable to be larger-scaled. As throughputs of electronic machines and instruments, etc. have been recently increased, DRAMs used in electronic machines and instruments have been rapidly micronized and larger-scaled.
Steps of a conventional DRAM fabrication method up to the step of forming bit contacts will be explained with reference to FIGS. 12 to 14. FIGS. 12 to 14 are sectional views of the DRAM in the steps of the method, which show the method. The views of FIGS. 12 to 14 are sectional views in the direction of a bit line.
First, a gate insulation film 102 of a silicon oxide film of, e.g., a 5 nm-thickness is formed on a silicon substrate 100 by, e.g., thermal oxidation.
Next, an amorphous silicon film 104 of, e.g., a 70 nm-thickness, a tungsten film 106 of, e.g., a 45 nm thickness, and a silicon nitride film 108 of, e.g., a 200 nm-thickness are sequentially deposited on the entire surface by, e.g., CVD (Chemical Vapor Deposition).
Next, these films are patterned in the same shape by lithography and etching. Thus, the gate electrode 112 having the upper surface covered by the silicon nitride film 108 and having the amorphous silicon film 104 and the tungsten film 106 laid one on the other is formed.
Next, with the gate electrode 112 as a mask, ion implantation is performed to form a source/drain diffused layer 114a, 114b in the silicon substrate 100 on both side of the gate electrode 20 (FIG. 12A).
Thus, a memory cell transistor including the gate electrode 112, the source/drain diffused layer 114a, 114b is formed on the silicon substrate 100.
Next, a silicon nitride film 116 of, e.g., a 20 nm-thickness is formed on the entire surface by, e.g., CVD (FIG. 12B).
Next, anisotropic etching is performed until the silicon substrate 100 is exposed to form a spacer insulation film 118 of the silicon nitride film on the side wall of the gate electrode 112 (FIG. 12C).
Then, a barrier insulation film 120 of a silicon nitride film of, e.g., a 15 nm-thickness is formed on the entire surface by, e.g., CVD (FIG. 13A).
Then, an inter-layer insulation film 122 of a BPSG (Boro-Phospho-Silicate Glass) of, e.g., an about 350 nm-thickness is formed on the entire surface by, e.g., CVD (FIG. 13B).
Next, a step of the inter-layer insulation film 122 on the upper surface thereof is decreased by, e.g., reflow, and then the upper surface of the inter-layer insulation film 122 is polished until the silicon nitride film 108 is exposed, to be planarized (FIG. 13C).
Next, a contact hole 124 is formed by lithography and etching down to the source/drain diffused layer 114a in the inter-layer insulation film 122 and the gate insulation film 102 by self-alignment with the gate electrode 112 and the barrier insulation film 120 (FIG. 14A).
Then, a plug of amorphous silicon is buried in the contact hole 124 opened in the inter-layer insulation film 122 (FIG. 14B). For example, an amorphous silicon film is deposited by, e.g., CVD and then etched back until the silicon nitride film 108 is exposed, to be thereby left selectively in the contact hole 124. Thus, the plug 126 is formed in the contact hole 124.
Next, inter-layer insulation films 128a, 128b are sequentially formed of, e.g., silicon oxide film, etc. on the entire surface by, e.g., CVD.
Next, a contact hole 130 is formed down to the plug 126 in the inter-layer insulation films 128a, 128b by lithography and etching.
Then, a bit line 132 is formed on the inter-layer insulation film 128b, connected to the plug 126 through the contact hole 130 (FIG. 14C).
As described above, in the conventional DRAM fabrication method, the so-called self-alignment contact technique that the silicon nitride film 108 formed on the gate electrode 112, and the spacer insulation film 118 and the barrier insulation film 120 formed on the side wall of the gate electrode 112 are used as a stopper in opening the contact hole 120 has been widely used. Such self-alignment contact technique is widely used in fabricating not only DRAMs but also other memory devices, such as SRAMs, logistic devices, etc.
However, the sidewall insulation film formed of the space insulation film 118 and the barrier insulation film 120 on the side wall of the gate electrode have been becoming thinner with recent more micronization of semiconductor devices for higher integration. Such thinning of the sidewall insulation film causes capacitance increase between interconnection layers and between interconnection layers and plugs. Even in a case that a metal material of low resistivity is used as a material forming the gate electrode, signal delay due to such parasitic capacitances have spoiled the merits of such metal material.
It will be means for solving the above-described problem to make the sidewall insulation film as thick as possible in forming the sidewall insulation film. However, the sidewall insulation film is simply made thick, whereby a gap between adjacent sidewall insulation film is made small, which makes it difficult to form the contact hole between the layers. That is, when the sidewall insulation film is made thick, a gap 134 between the barrier insulation film 120 is made small as exemplified in FIG. 15. Such small gap 134 does not admit a reactive gas for the etching to remove the barrier insulation film 120 at the bottom of the gap 134 so as to form the contact hole to arrive at the side wall of the gap 134. As a result, it is difficult to form the contact hole.
When the gap 134 is small, a contact area where the plug 126 and the bit line 130 contact each other is made small, which results in contact resistance increase.
Furthermore, at actual fabrication sites, it is necessary to ensure margins for fabrication deflections. Accordingly, the gap 134 will be made smaller.